Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
READ to WRITE Command Interval
CAS latency=2
T0
T1
T3
T4
T6
T8
T2
T5
T7
CLK
Read
Write
Command
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
Burst length=8, CAS latency=2
T8 T9
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Command
DQM
Write
Read
Q2
D2
Q0
Q1
D0
D1
DQ
Hi-Z is
necessary
example: Burst length=4, CAS latency=3
T6
T0
T1
T3
T8
T2
T4
T5
T7
CLK
Command
Read
Write
DQM
DQ
Q2
D0
D2
D1
Hi-Z is
necessary
The minimum command interval = (4+1) cycles
Document : 1G5-0127
Rev2
Page24