VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
VIS
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
*BS0
A10
RAa
CAa
RAa
ADD
DQM
Hi-Z
DAa0
DAa1
DAa2
DAa3
DQ
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Clock
Suspended
1 Cycle
Activate
Command
Bank A
Write
Command
Bank A
* BS1=”L”, Bank C,D = Idle
Document :1G5-0177
Rev.2
Page38