VIS
Parameter
Sym-
bol
Min
CLK cycle time
CL = 3
CL = 2
CLK to valid output
delay
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold
time
CL = 3
CL = 2
CL = 3
CL = 2
t
CK3
t
CK2
t
AC3
t
AC2
t
CH
t
CL
t
CKS
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH3
t
OH2
t
LZ
t
HZ
t
RC
t
RAS
t
RCD
t
RP
t
RRD
t
DPL
t
T
t
RSC
t
REF
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.5
2.5
0
2.5
60
42
18
15
12
12
1
2
64
10
100K
5
6
7.5
5
6
-6
*1
Max
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
±
0.3V , V
SS
= V
SSQ
= 0V, unless otherwise noted)
Limits
-7
Min
7
7.5
5.4
6
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
2.7
0
2.7
63
42
20
15
14
14
1
2
64
10
100K
5.4
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.7
3
0
2.7
67.5
45
20
20
15
15
1
2
64
10
100K
5.4
Max
Min
7.5
10
5.4
6
3
3
2
1
2
1
2
1
2
1
3
3
0
3
70
50
20
20
20
20
1
2
64
10
100K
6
-7L
Max
Min
8
10
6
6
-8H
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tck
ms
*2
*2
*2
*2
Unit
Note
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS to CAS delay
Row precharge time
Row active to active delay
Data in to precharge
Transition time
Mode reg. set cycle
Refresh time
Notes
1. -6 grade is available only on 4MX16 option.
2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Document :1G5-0177
Rev.2
Page 8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
