Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
High level
is required
RSC
Minimum of 2 Refresh Cycles are required
CS
RAS
CAS
WE
BS
A10
Address Key
ADD
DQM
High Level is Necessary
t
t
RC
RP
Hi-Z
DQ
2nd Auto
Refresh
Command
Command
Register
Set Command
Precharge
Command
All Banks
Mode
1st Auto
Refresh
Command
Inputs
must
be stable
for 100us
Document : 1G5-0127
Rev2
Page34