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VG36641641BT 参数 Datasheet PDF下载

VG36641641BT图片预览
型号: VG36641641BT
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS同步动态RAM [CMOS Synchronous Dynamic RAM]
分类和应用:
文件页数/大小: 70 页 / 973 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
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Preliminary  
VG36641641BT  
CMOS Synchronous Dynamic RAM  
VIS  
8.2 Write with Auto Precharge  
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.)  
after the last data word input to the device.  
WRITE with AUTO PRECHRGE  
Burst lengh = 4  
T0  
T1  
T3  
T6  
T8  
T2  
T4  
T5  
T7  
CLK  
No New Command to Bank B  
AUTO PRECHARGE starts  
Command  
WRITA B  
DB0  
t
DPL  
CAS latency = 2  
Hi - Z_  
DQ  
DB2  
DB3  
DB1  
No New Command to Bank B  
AUTO PRECHARGE starts  
Command  
WRITA B  
DB0  
t
DPL  
CAS latency = 3  
Hi - Z  
DQ  
DB2  
DB1  
DB3  
Remark WRITA means WRITE with AUTO Precharge  
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data  
word is valid.  
In the table below, minus means clocks before the reference; plus means clocks after the reference.  
CAS latency  
2
Read  
-1  
Write  
+ tDPL(min.)  
3
-2  
+ tDPL(min.)  
9.Read/Write Command Interval  
Document : 1G5-0127  
Rev2  
Page19  
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