Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
5.Mode Register (Address Input for Mode Set)
13
0
6
12
0
10
0
7
1
3
11
0
9
0
8
0
4
2
1
5
5
0
0
0
JEDEC Standard Test Set
Reserved
12
x
1
11 10
x
x
13
x
8
0
3
WT
2
9
1
7
0
6
6
4
Burst Read and Single Write (for Write Through Cache)
LTMODE
BL
13
x
1
12 11
x
10
x
8
0
5
3
WT
9
0
7
0
4
2
Burst Read and Burst Write
X = Don’t care
x
BL
LTMODE
Bits2 - 0
WT = 1
1
WT = 0
1
000
001
010
011
100
101
110
111
2
4
2
4
8
8
Burst length
R
R
R
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6 - 4
000
CAS Iatency
R
R
2
001
010
011
100
101
110
111
3
Latency
mode
R
R
R
R
Remark R : Reserved
Document : 1G5-0127
Rev2
Page14
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
