VIS
symbol
t
CH
t
CL
t
T
t
CK3
t
CK2
t
IS
t
IH
t
LZ
t
HZ3
t
HZ2
t
AC3
t
AC2
t
OH
t
RCD
t
RRD
t
CCD
t
WR
t
RAS
t
RP
t
DAL3
t
DAL2
t
RC
t
RSC
t
REF
t
SRX
t
BDL
t
PDE
Access time from CLK
(positive edge)
Data output hold time
RAS to CAS delay
Row activate to row activate delay
CAS to CAS Delay time
Write recovery time
Row activate to precharge time
Precharge to refresh/row activate
command
A.C. Parameter
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
A.C Characteristics:
Test Conditions:
(Ta=0 to 70°C V
DD
=3.3V
±
0.3V ,V
SS
=0V)
-5.5
Min.
Clock high time
Clock low time
Transition time (Rise and Fall)
Clock cycle time
CL* = 3
CL* = 2
Data/Address/Control Input setup time
Data/Address/Control Input hold time
Data output low impedance
Data output high impedance CL* = 3
CL* = 2
CL* = 3
CL* = 2
2.2
16.5
11
1
1t
CK
+2
ns
33
16.5
100,000
2
2
0.5
5.5
8
2
1
1
4.5
6
5
7
2.5
18
12
1
1t
CK
+2
ns
36
18
2clk+
t
RP
1clk+
t
RP
54
2
64
1
1
5
1
1
5
64
1
1
5
100,000
10
Max.
Min.
2
2
0.5
6
8.5
2
1
1
5
6.5
5.5
7
2.5
20
14
1
1
40
20
2clk+
t
RP
1clk+
t
RP
62
2
64
1
1
6
2clk+
t
RP
1clk+
t
RP
72
2
64
ns
CLK
ms
CLK
CLK
ns
100,000
10
-6
Max.
Min.
2.5
2.5
0.5
7
10
2
1
1
5
7
6
7
2.5
20
16
1
1
48
100,000
20
CLK
CLK
10
-7
Max.
Min.
3
3
0.5
8
12
2
1
1
7
8
7
8
9
10
-8
Max.
unit
note
ns
ns
ns
Data-in to ACT (REF) Command (CL = 2clk+
3)
t
RP
Data-in to ACT (REF) Command (CL = 1clk+t
RP
2)
Row cycle time
(Special) Mode Register Set Cycle time
Refresh time
Minimum CKE ”High”for Self-Refresh
exit
Last data in to burst STOP command
Power Down Exit set-up time
55
2
Document:1G5-0160
Rev.1
Page 6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
