VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
VIS
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
ADD
DQM
t
t
t
RCD
DPL
RP
Hi-Z
QAa5
QAa0
Write
QAa4
QAa6 QAa7 QBa0 QBa1 QBa2
Precharge
QAb2
QAb3 QAb4
QAb0 QAb1
DQ
QAa1 QAa2
QBa3 QBa4
QBa6 QBa7
QBa5
QAa3
Activate
Command
Bank A
Write
Command
Bank A
Active
Command
Bank A
Activate
Command
Bank B
Command
Bank A
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183
Rev.1
Page47