TIMESTREAM
TM
PRODUCT FAMILY
VSC9187
VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
Compliant with SONET Requirements as Stated in ANSI
T1.105 and Bellcore GR-253-CORE
Facilitates Hardware Based UPSR Switching in
Accordance with Telcordia GR-1400-CORE
Thermally Enhanced 360 CCGA Package
IEEE P1149.1 Test Access Port
S P E C I F I C AT I O N S :
F E AT U R E S :
3024x3024 (5 G) Non-Blocking VT1.5 TSI, 6048x6048 (10 Gb/s)
VT1.5 TSI with 2:1 UPSR Input Pre-selection
2x9x622 Mb/s STS-12 LVDS Backplane Inputs with Integrated
Retiming and Alignment
Working and Protection 2 x 9 x 622 Mb/s STS-12 LVDS Outputs
Supports 2:1 Hardware VT1.5 UPSR Selection when used in
Conjunction with VSC9188 VT1.5 Pointer Processor and
Column Aligner
6 Service & 6 Protection STS-1 like Serial 51.84 Mb/s
Interfaces for Local Drop Interfaces
Integrated STS-1 Frame Delay Management on Output for
use in Subtended STS-1 Switch Fabrics
2.5/1.8V Power Supply; 0.18um Technology
A P P L I C AT I O N S :
VT1.5 Time Slot Interchange (TSI)
BENEFITS:
Low cost, low power, VT1.5 switching
K E Y S P E C I F I C AT I O N S :
PARAMETERS
Vdd_core
Vdd_IO
POWER DISSIPATION
IDD_2.5
IDD_1.8
PD_typical
PD_peak
Data STS-12 Inputs I/O
Service Data STS-1 Inputs I/O
STS1 Reference Clock Input
Peak power supply current from 2.5V VDD
Peak power supply current from 1.8V VDD
Typical power dissipation
Peak power dissipation
622Mb/s LVDS
51.84Mb/s LVDS
51.84MHz LVDS
–
–
51.83MHz
0.4 A
2.25 A
4W
5W
–
–
51.85MHz
Nominal
Nominal
Nominal
DESCRIPTION
Voltage for Core
Voltage of IO cells
Min
1.65V
2.3V
Max
1.95V
2.7V
Conditions
Recommended 1.8V
Recommended 2.5V
PB-VSC9187-001
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
