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VSC9182XX 参数 Datasheet PDF下载

VSC9182XX图片预览
型号: VSC9182XX
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital Time Switch, PBGA480, 37.50 MM, TBGA-480]
分类和应用: 电信电信集成电路
文件页数/大小: 4 页 / 39 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Product Brief
VSC9182 - Timberline
Features
• 64x64 STS-12/STM-4 TSI switch with non-
blocking 768x768 STS-1 switch matrix
• Supports both multicast and broadcast
• Serial LVDS 622 Mb/s high-speed interface
with PECL/CML compatibility and retiming
• 50MHz 11-bit microprocessor interface
• IEEE P1149.1 test access port
• Compatible with VSC9184 ADM & Pointer
Processor and VSC9180 Hitless Backplane
Tranceiver
TimeStream Product Family
64x64 STS-12/STM-4 TSI Switch Fabric
• Integrated clock synthesis with a choice of two
reference frequencies
• LOS Detection, input parity checking & output
parity insertion; scrambling & descrambling
• Hitless reconfiguration of TSI mapping
• Single +3.3V Power Supply
• Compliant with SONET and SDH requirements
as stated in ANSI T1.105, Bellcore GR-253-
CORE and ITU-T G.707 documents
• Thermally Enhanced 37.5mm 480 BGA Package
Functional Diagram
Time Slots In
1L
1C
2C
3C
64C
1B
2B
3B
64B
1A
CPU i/f
1B
Time Slots Out
3A
1C
3B
64C
3C
1B
1B
64B
3D
Channels Out
Channels In
2L
3L
64L
2A
3A
64A
VSC
9182
1A
2B
64D
1D
4B
2C
VSC9182 Block Diagram
SYNCP/N
FOSYNCP/N
RXD[63..0]+/-
indexer
input
backplane
interfaces
(64)
Clock
Data
Interconnection
Matrix
and Storage
Data
output
backplane
interfaces
(64)
TXD[63..0]+/-
SYSCLKP/N
Clock
Synthesis
PLL
Control
CPU
Interface
Control
Test
Interface
CKSEL
PLOCK
D[9..0]
A[10..0]
ALE
CSB
WRB
RDB
CONFIG
INTB
PARITYON
SCRMBL
CKBYP
IDDQ1
IDDQ2
G52289-0, Rev 1.0
12/7/99
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
TDI
TCK
TMS
TRSTB
TDO
RSTB
MODE8
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