VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
PLL locked to reference clock.
Minimum 5 CLK16 cycles
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
Figure 2: Enabling FIFO Operation
FIFO Mode Operation
Transparent Mode Operation
RESET
Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.
Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-
V
CC
VSC8169
Split-end equivalent termination is Z
O
to V
TERM
R1 = 125
Ω
R2 = 83
Ω
, Zo=50
Ω
, V
TERM
= V
CC
-2V
R1
R1
Z
o
Z
o
R1||R2 = Z
O
V
CC
R2 + V
EE
R1
R1+R2
= V
TERM
R2
R2
V
EE
Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-
VSC8169
Z
O
Z
O
50
Ω
V
CC
-2V
50
Ω
G52230-0, Rev 3.6
01/02/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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