VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Package Information
208 TBGA Package Drawings
17 15 13 11
9
5
1
7
3
0.10
10
14 12
8
10
6
4
2
16
D
-A-
A
B
D
F
11
CORNER
C
E
-B-
G
H
K
M
P
J
L
N
R
E
T
U
e
DETAIL B
D1
45 DEGREE 0.5MM CHAMFER
(4 PLCS)
BOTTOM VIEW
TOP VIEW
DETAIL A
0.30
0.10
S
S
C
C
A S B S
b
4
SIDE VIEW
DETAIL B
A1
c
A
c c c
c
-C-
P
DETAIL A
6
aaa C
5
DIMENSIONAL REFERENCES
NOM.
1.55
0.65
MAX.
1.65
0.70
REF.
A
A1
D
D1
MIN.
1.45
0.60
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH.
22.80
23.00
20.32 (BSC.)
23.20
3. "M" REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE,
AND SYMBOL "N" IS THE MAXIMUM ALLOWABLE NUMBER OF
BALLS AFTER DEPOPULATING.
22.80
23.00
23.20
E
E1
b
c
M
N
aaa
ccc
e
20.32 (BSC.)
0.75
4. "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
PARALLEL TO PRIMARY DATUM -C- .
0.65
0.85
0.85
0.95
5.
DIMENSION "aaa" IS MEASURED PARALLEL TO PRIMARY DATUM -C- .
0.90
17
208
6. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
7. PACKAGE SURFACE SHALL BE BLACK OXIDE.
8. CAVITY DEPTH VARIOUS WITH DIE THICKNESS
0.25
0.25
9. SUBSTRATE MATERIAL BASE IS COPPER.
1.27 TYP.
10. BILATERIAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF PACKAGE BODY
11. 45 DEG. 0.5 MM CHAMFER CORNER AND WHITE DOT FOR PIN1 IDENTIFICATION
P
0.15
G52251-0, Rev. 4.0
9/6/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 31
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