VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH
Clock and Data Recovery IC
Data Sheet
VSC8122
Functional Description
Data Input
The data input receiver is internally terminated by a center-tapped resistor network. For differential input
AC coupling, the network is terminated to the appropriate termination voltage, V
TERM
through a blocking
capacitor, C
AC
to ground. The input requires a differential signal with a peak-to-peak voltage on both the true
and complement of a minimum of 250mV. These inputs are required to be AC-coupled to allow use with a vari-
ety of limiting amplifiers.
Figure 1: Input Termination (AC-Coupled)
Limiting Amp
Z
o
= 50Ω
0.1
µF
VSC8122
DI+
50Ω
C
AC
V
TERM
50Ω
Z
o
= 50Ω
0.1
µF
DI-
High-Speed Clock and Data Outputs
The VSC8122 high-speed clock and data outputs can be DC-terminated, 50
Ω
to V
CC
as indicated in
Figure 2.
Figure 2: High-Speed Clock and Data Output DC Termination
VSC8122
V
CC
V
CC
100Ω
CO+ / DO+
Z
o
= 50Ω
50Ω
CO- / DO-
100Ω
Z
o
= 50Ω
50Ω
V
CC
V
CC
Page 2
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52228-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
