VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8122
Table 2: Reference Frequency
Reference Frequency
19.44MHz (19.53MHz)
38.88MHz (39.06MHz)
77.76MHz (78.13MHz)
155.52MHz (156.25MHz)
Multi-Rate SONET/SDH
Clock and Data Recovery IC
REF_SEL0
0
1
0
1
REF_SEL1
0
0
1
1
Loop Filter
The Phase-Lock Loop (PLL) on the VSC8122 employs two external capacitors. The PLL design is fully
differential, therefore the loop filter must also be fully differential. One capacitor should be connected between
FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are
low-inductance 1.0
µ
F (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater, with tolerance of 10%
or better.
AC Characteristics
(Over recommended operating conditions)
Table 3: AC Characteristics
Parameters
t
pd
t
r
,t
f
t
r
,t
f
Jitter
gen
Jitter
tol
LBW
Jitter
peak
Description
Center of output data eye from
rising edge of CO+
DO± rise and fall times
CO± rise and fall times
Jitter Generation (12kHz-
20MHz)
Jitter Tolerance
Loop Bandwidth
Jitter Peaking
Min
-75
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
Max
+75
150
135
3.6
—
2.0
0.1
Units
ps
ps
ps
Conditions
20% to 80% into 50Ω load.
20% to 80% into 50Ω load.
Measured at the HS data output for
ps - rms jitter in the 12kHz - 20MHz band.
Assume 1.2ps rms input data jitter.
—
MHz
dB
Exceeds SONET/SDH mask
-3dB point of jitter transfer curve
G52228-0, Rev 4.1
01/05/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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