VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.488GHz SONET/SDH
Clock Generator
VSC8121
Reference Clock Input
The input stage at the REFCLK input pin consists of ESD protection, followed by a current limiting circuit
which precedes a driver responsible for providing the signal to the phase frequency detector. As pictured below
in Figure 4, the driver has a high impedance, FET gate input. The additional resistance contributed by the cur-
rent limiting circuit is relatively negligible.
Figure 4: Reference Clock Input Diagram
VCC
Current
Limiting
REFCLK
VTT
VEE
Care should be taken in selection of the reference clock. Time jitter on the reference clock which is within
the PLL’s loop bandwidth will appear on the 2.5GHz output. Telecom quality crystal oscillators from vendors
such as Connor-Winfield or Vectron are suitable.
Table 1: Reference Clock Selection
Selected Reference
Frequency
Typical
Loop Bandwidth
REFSEL[1]
REFSEL[0]
0
0
0
1
51.84MHz
77.76MHz
155.52MHz
2500KHz
3000KHz
5500KHz
1
Don’t Care
Die Usage
Vitesse optionally provides this device in unpackaged, die-only format for multi-chip module and related
applications. For further informtion, please contact Vitesse.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 4
G52163-0, Rev 4.2
04/16/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
