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VSC8117 参数 Datasheet PDF下载

VSC8117图片预览
型号: VSC8117
PDF下载: 下载PDF文件 查看货源
内容描述: ATM / SONET / SDH 155分之622 Mb / s的收发器复用/解复用,集成时钟发生器和时钟恢复 [ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery]
分类和应用: 时钟发生器异步传输模式ATM
文件页数/大小: 22 页 / 408 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8117
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). The low-speed trans-
mit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are mux’d into the low-speed byte wide receive output bus
(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
Figure 5: Split Loopback Datapath
RXDATAIN
Recovered
Clock
CRU
D
Q
1:8
Serial to
Parallel
D
Q
RXOUT[7:0]
0
1
Q
D
8:1
Parallel to
Serial
÷8
Q
D
RXCLKIN
DSBLCRU
TXDATAOUT
RXLSCKOUT
TXIN[7:0]
TXLSCKIN
PLL
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
Clock Synthesis
The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (pin CMUFREQSEL
selects the divide-by ratios of 8 or 32, see Table 10) and the reference clock. The integrator provides a transfer
function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00