VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Figure 4: Equipment Loopback Data Path
RXDATAIN
D Q
0
1
1:8
Serial to
Parallel
D
Q
RXOUT[7:0]
RXCLKIN
TXDATAOUT
Q
D
0
1
÷
8
8:1
Parallel to
Serial
Q
D
RXLSCKOUT
TXIN[7:0]
EQULOOP
PLL
÷
8
TXLSCKOUT
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and
facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized
and presented to RXOUT[0:7], and TXIN[0:7] will not be serialized and present to TXDATAOUT.
Figure 5: Split Loopback Datapath
1:8
Serial to
Parallel
D
Q
RXDATAIN
D
Q
0
1
RXOUT[7:0]
RXCLKIN
1
0
1
Q
D
÷
8
8:1
Parallel to
Serial
Q
D
RXLSCKOUT
TXIN[7:0]
TXDATAOUT
0
1
0
PLL
EQULOOP
FACLOOP
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
G52220-0, Rev 4.1
1/8/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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