VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
VSC8116
Package Pin Description
Signal
RESET
Pin
I/O
Level
Pin Description
1
I
I
TTL
TTL
TTL
+3.3V
PECL
PECL
-
Resets frame detection, dividers, controls; active high
Enable loop timing operation; active HIGH
Reference clock frequency select, refer to table 2
+3.3V Power Supply
LOOPTIM0
CMUFREQSEL
VDD
2
3
I
4
P
O
O
-
TXDATAOUT+
TXDATAOUT-
N/C
5
Transmit output, high speed differential data +
Transmit output, high speed differential data -
No connection
6
7
RXCLKIN+
RXCLKIN-
VDD
8
I
PECL
PECL
+3.3V
TTL
-
Receive high speed differential clock input+
Receive high speed differential clock input-
+3.3V Power Supply
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
P
I
OOF
Out Of Frame; Frame detection initiated with high level
No connection
N/C
-
RXDATAIN+
RXDATAIN-
VDD
I
PECL
PECL
+3.3V
-
Receive high speed differential data input+
Receive high speed differential data input-
+3.3V Power Supply
I
P
-
N/C
No connection
N/C
-
-
No connection
VDD
P
O
O
P
O
O
O
O
O
O
P
O
O
P
-
+3.3V
TTL
TTL
GND
TTL
TTL
TTL
TTL
TTL
TTL
GND
TTL
TTL
+3.3V
-
+3.3V Power Supply
RXOUT0
RXOUT1
VSS
Receive output data bit0
Receive output data bit1
Ground
RXOUT2
RXOUT3
RXOUT4
RXOUT5
RXOUT6
RXOUT7
VSS
Receive output data bit2
Receive output data bit3
Receive output data bit4
Receive output data bit5
Receive output data bit6
Receive output data bit7
Ground
RXLSCKOUT
FP
Receive byte clock output
Frame detection pulse
VDD
+3.3V Power Supply
N/C
No connection
LOSTTL
VDD
I
TTL
+3.3V
GND
TTL
GND
Loss of Signal Control - TTL input; active low
+3.3V Power Supply
P
P
I
VSS
Ground
REFCLK
VSSA
Reference clock input, refer to table 2
Analog Ground (CMU)
P
G52220-0, Rev 4.1
1/8/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
