VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
VSC8115
DC Characteris tics
Table 4: LVPECL Single-ended Inputs and Outputs
Parameters
VIH
Description
Min
Typ
—
Max
Units
V
Conditions
Guaranteed Input HIGH
Voltage
Input HIGH voltage
VDD - 1.125
VDD - 0.5
Guaranteed Input LOW
Voltage
VDD - 2.0
—
VDD - 1.5
V
VIL
Input LOW voltage
-0.5
-0.5
—
—
—
—
10
mA
mA
V
IIH
IIL
Input HIGH current
Input LOW current
Output LOW voltage
Output HIGH voltage
VIN = VDD - 0.5V
VIN = VDD - 2.0V
50W to (VDD - 2V)
50W to (VDD - 2V)
10
VDD - 2.0
VDD - 1.25
VDD - 1.8
VDD - 0.67
VOL
VOH
V
Table 5: LVPECL Differential Inputs
Parameters
VIH
Description
Min
Typ
Max
Units
Conditions
Input HIGH
voltage
Guaranteed Input
HIGH Voltage
VDD - 1.75
—
—
—
—
—
VDD - 0.45
V
V
Input LOW
voltage
Guaranteed Input
LOW Voltage
VIL
DVIN
IIH
VDD - 2.0
250
VDD - 0.7
Differential
Input Voltage
—
10
10
mV
mA
mA
—
Input HIGH
current
-0.5
DVIN = 0.5V
DVIN = 0.5V
Input LOW
current
IIL
-0.5
G52272-0, Rev. 1.1
9/29/00
Ó VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
