VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8114
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
sion of the input reference clock. External control input REFSEL selects the multiply ratio of the CMU (see
table 11). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit
interface of the UNI device to the transmit input registers on the VSC8114 (see Application Notes, p. 20).
Figure 1: Data and Clock Transmit Block Diagram
VSC8114
PM5355
TXDATAOUT+
TXDATAOUT-
Q D
Q D
TXIN[7:0]
Q D
TXLSCKIN
REFCLK
CMU
Divide-by-8
TXLSCKOUT
Receive Section
High speed Non-Return to Zero (NRZ) serial data at 622Mb/s are received by the RXDATAIN inputs. The
CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-wide parallel
data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT)
should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The
on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input data and corre-
sponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN is clocked in
on the rising edge of RXCLKIN+. See Figure 2.
The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8114 will con-
tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When
a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high.
Loss of Signal
The VSC8114 features Loss of Signal (LOS) detection. Loss of Signal is detected if the incoming serial
data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8114
forces the receive data low which is an indication for any downstream equipment that an optical interface failure
has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK
unless DSBLCRU is active, in which case it will be clocked by the CMU. This LOS condition will be removed
when the part detects more than 16 transitions in a 128 bit time window. This LOS detection feature can be dis-
abled by applying a high level to the LOSDETEN_ input. The VSC8114 also has a TTL input LOSTTL and a
G52185-0, Rev 4.0
11/1/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
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