VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
VSC8114
with Integrated Clock Generation and Clock Recovery
Figure 10: Transmit High Speed Data Timing Diagram
TTXDAT
TXDATAOUT+
TXDATAOUT-
Table 5: Transmit High Speed Data Timing Table
Parameter
Description
Min
Typ
Max
Units
TTXDAT
Transmit data width
-
1.608
-
ns
Figure 11: Transmit Data Timing Diagram
TPROP
TXLSCKOUT
TCLKIN
TXLSCKIN
TINH
TINSU
TXIN [7:0]
TXINP
TERR
TXPERR
Table 6: Transmit Data Input Timing Table
Parameter
Description
Min
Typ
Max
Units
TCLKIN
Transmit data input byte clock period
-
12.86
-
ns
Transmit data and parity setup time with respect to
TXLSCKIN
TINSU
TINH
TPROP
TERR
1.0
1.0
-
-
-
-
ns
ns
Transmit data and parity hold time with respect to
TXLSCKIN
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
-
-
-
3.5
9.0
ns
ns
Propagation delay from TXLSCKIN to TXPERR
3.2
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Page 10
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52185-0, Rev 4.0
11/1/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
