VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Table 4: Transmit Data Input Timing Table (STS-12 Operation)
Parameter
Description
Min
Typ
Max
Units
TCLKIN
TINSU
TINH
Transmit data input byte clock period
-
12.86
-
-
-
ns
ns
ns
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
1.0
1.0
-
-
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
TPROP
-
-
3.5
ns
Table 5: Transmit Data Input Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TCLKIN
TINSU
TINH
Transmit data input byte clock period
-
51.44
-
-
-
ns
ns
ns
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
1.0
1.0
-
-
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
TPROP
-
-
30
ns
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Figure 10: Receive Data Output Timing Diagram
TRXCLKIN
RXCLKIN+
RXCLKIN-
TRXLSCK
RXLSCKOUT
RXOUT [7:0]
A1
A2
A2
A2
A2
Table 6: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
TRXLSCK
Receive clock period
-
-
1.608
12.86
-
-
ns
ns
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
TRXVALID
TPW
4.0
-
-
-
-
ns
ns
Pulse width of frame detection pulse FP
12.86
G52154-0, Rev 4.2
3/19/99
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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