VSC8101/8102
VITESSE
155.52 Mb/s Clock and
Data Recovery Units
Preliminary Data Sheet
VSC8101/8102 AC Characteristics (Over recommended operating range
Parameter
Description
Min
Typ
Max
Units
tCLK
REFCK+/- Input Clock period(1)
—
6.43
—
ns
tCLK
30 ppm
-
tCLK +
30 ppm
tDCYC
SDAT +/- Input data period
—
SDAT+/- Input Rate Difference with respect to
REFCK+/-
∆ fDC
tCDC
tDH
-30
40
—
—
—
+30
60
ppm
%
REFCK+/- Duty Cycle
Recovered Data hold time from falling edge of
Recovered Clock(2)
2.5
3.9
ns
Recovered Data setup time to falling edge of
Recovered Clock(2)
tDS
2.5
—
3.9
ns
t
RCLK+/- Recovered Clock Output High Pulse Width
RCLK+/- Recovered Clock Output Low Pulse Width
RCLK+/- Recovered Clock Period
2.6
2.6
6.0
—
—
—
—
—
ns
ns
ns
RCH
t
RCL
t
6.8
RCYC
SDAT+/- Input JitterAccommodation (DC to 20 MHz)
Peak-to-peak
tDJA
—
—
—
—
3.2
5.0
ns
(3)
tLA
Lock Acquisition Time
µ s
Loop Bandwidth:
a) at FILTER0 = Lo
b) at FILTER0 = Hi
fBW
—
—
150
10
KHz
tRCJ
RCLK+/- Recovered Clock Jitter
-400
—
400
ps
ps
Propagation Delay from SDATA+/- Input to RDAT+/-
Output
tPD
—
TBD
tCr tCf
REFCK+/- Input rise and fall time, 20% to 80%
SDATA+/- Input rise and fall time, 20% to 80%
—
—
—
—
1.2
1.2
ns
ns
,
tSDr tSDf
,
RCLK+/- Recovered Clock Output rise and fall time,
20% to 80%
tRCr tRCf
300
300
—
—
800
800
ps
ps
,
RDAT+/- Recovered Data Output rise and fall time,
20% to 80%
tRDr tRDf
,
Notes: (1) The part is designed to operate at 155.52 MHz. A reference clock with frequency variation of +/- 50 ppm or better is rec-
ommended. Consult the factory for applications other than this frequency.
(2) With minimum 50% Input Data Eye opening at 155.52 Mb/s.
.
(3) With a jitter-free data input and minimum transition density of 50%.
G52087-0 Rev. 1.3
® VITESSE Semiconductor Corporation
Page 3
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