VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8061/VSC8062
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8062 Demultiplexer AC Characteristics
(Over recommended operating range)
Figure 6: VSC8062 Timing Diagram
CLK (CLKN)
High-speed differential clock input
t
CLK
DI (DIN)
High-speed serial data input
CLK16
Parallel data clock output
t
D
t
BD
t
D
Demultiplexed Parallel
Data Outputs
D0
D1
D15
Table 2: VSC8062 AC Characteristics
Parameter
t
CLK
t
D
t
DSU
Clock period
(1)
BYTE CLK16 period (t
CLK
x 16)
CLK16 falling edge output to valid data
t
SU
+
t
H
Phase Margin =
1 – ------------------
×
360°
-
t
CLK
Serial data phase timing margin with respect to
high-speed clock
(2)
Description
Min
400
6.4
1.0
Typ
Max
Units
ps
ns
Conditions
3.0
ns
t
DH
180
(3)
degrees
NOTES: (1) If t
CLK
changes, all remaining parameters change as indicated by the equations.
(2) t
SU
and t
H
are setup and hold times of the serial data input register.
(3) At t
CLK
= 400ps.
G52069-0, Rev 4.3
05/11/01
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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