VSC7961
Data Sheet
F
UNCTIONAL
D
ESCRIPTION
The VSC7961 is a high-speed limiting amplifier with LOS detect. The VSC7961 is designed to operate with a +3.3V
or +5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The VSC7961 has PECL outputs
(the VSC7959 provides the same functionality as the VSC7961 with CML outputs). Key features of the VSC7961 are
LOS detect, output offset correction, output squelch, low power supply current, and fast rise/fall times.
The inputs of the VSC7961 provide 100Ω input impedance between IN+ and IN– and are intended to be AC-coupled.
The PECL output circuits should be terminated through 50Ω to V
CC
– 2V. If the outputs are to be AC-coupled, the
VSC7959 is the preferred device as it will dissipate less power.
LOS Detect
The LOS Detect feature utilizes an rms power detector with programmable LOS indicator to provide two outputs,
LOS and LOS. The input, TH, is used to set the threshold at which the LOS detector outputs, LOS and LOS, change
state. See
Table 3, “Loss of Signal Specifications” on page 3
for setting the resistor value between TH and ground.
Table 4, “Loss of Signal Truth Table” on page 3
clarifies the interaction of LOS and SQUELCH.
Optional Squelch
Squelch is disabled when SQUELCH is not connected or is set to TTL LOW level. When SQUELCH is set to TTL
HIGH level and LOS is asserted, the data outputs, OUT+ and OUT– are forced to static levels. If LOS is not asserted,
the outputs will not be squelched.
Offset Correction
The offset correction feature is provided to ensure that the offsets in the limiting amplifier, coupled with its gain, do
not cause the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a
low-frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low-
frequency cut-off is 200kHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low-frequency cut-off is
lowered to approximately 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open.
For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between CZ1
and CZ2. This maintains a one-decade separation between the lowest input frequency and the low-frequency cut-off.
The low-frequency cut-off of the offset correction loop is given by the following equation:
f
OC
= 43 / [2π * 35k (C
Z
+ 100pF)]
= 196 • 10
–6
/ (C
Z
+ 100pF)
= 196 • 10
–6
/ (0.1µF + 100pF)
= 1.96kHz
(EQ 1)
4 of 14
G52360, Rev 4.0
5/15/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
