VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s CML Limiting Amplifier with LOS Detect
VSC7959
Package Pin Descriptions
Figure 1: Pin Diagram
Top View
TSSOP-16 Package
CZ1
CZ2
GND
IN+
IN-
GND
LEVEL
TH
1
2
3
4
5
6
7
8
16
15
14
13
NC
SQUELCH
VCC
OUT+
OUT-
VCC
LOS
LOS
VSC7959
12
11
10
9
Table 5: Pin Identifications
Pin Name
CZ1
CZ2
GND
IN+
IN-
GND
LEVEL
TH
LOS
LOS
VCC
OUT-
OUT+
VCC
SQUELCH
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant
of offset correction loop. See
Detailed Description
section.
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant
of offset correction loop. See
Detailed Description
section.
Supply Ground
Noninverted Input Signal
Inverted Input Signal
Supply Ground
Output Current Level. This pin may either be connected to ground or left unconnected. Connecting
to ground causes output current to be 20mA. The output is 16mA when left unconnected. See
Detailed Description
section.
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted. See
Application Information
section.
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by
TH. See
Detailed Description
section.
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold programmed
by TH. See
Detailed Description
section.
Power Supply
Inverted Data Output
Noninverted Data Output
Power Supply
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT- are forced to static levels.
No Connection
Page 4
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52358-0, Rev 2.0
02/09/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
