VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7939
Detailed Description
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
The VSC7939 is a high-speed laser driver with Automatic Power Control. The device is designed to operate
up to 3.125Gb/s with a 3.3V or 5V supply. The data and clock inputs support PECL inputs as well as other
inputs that meet the common-mode voltage and differential voltage swing specifications. The differential pair
output stage is capable of sinking up to 60mA from the laser with typical rise and fall times of 60ps. This output
may be DC-coupled for 5V operation. To allow for larger output swings during 3.3V operation, the VSC7939
was designed to be AC-coupled to the laser cathode with a pull-up inductor for DC-biasing. This configuration
will isolate laser forward voltage from the output circuitry and will allow the output at OUT+ to swing above
and below the supply voltage V
CC
. The key features of the VSC7939 are Automatic Power Control, low power
supply current, and fast rise and fall times. The VSC7938 is another Vitesse laser drivers with similar features in
a 48-pin TQFP package. The VSC7938 does not have monitoring for modulation and bias currents. The
VSC7940 is a modified version of the VSC7939 capable of 100mA output currents.
Automatic Power Control
To ensure constant average optical power, the VSC7939 utilizes an Automatic Power Control loop. A pho-
todiode mounted in the laser package provides optical feedback to compensate for changes in average laser out-
put power due to changes that affect laser performance such as temperature and laser lifetime. The laser bias
current is adjusted by the APC loop according to the reference current set at APCSET by an external resistor.
An external capacitor at CAPC controls the time constant for the APC feedback loop. The recommended value
for CAPC is 0.1
µ
F. This value reduces pattern-dependent jitter associated with the APC feedback loop and
guarantees stability. Because the APC loop noise is internally filtered, APCFILT is not internally connected and
does not need to be connected to any external components. The device’s performance will not be affected if a
capacitor is connected to APCFILT. If the APC loop cannot adjust the bias current to track the desired monitor
current, FAIL is set low.
The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC
(0.1
µ
F) and a resistor must be connected at APCSET to set the average optical power. For open-loop operation
(no APC), a 100k
Ω
resistor should be connected between APCSET and GND. CAPC has no effect on open-
loop operation. In both modes of operation, resistors to ground should be placed at BIASMAX and MODSET to
set the bias and modulation currents.
Data Retiming
The VSC7939 provides inputs for differential PECL clock signals for data retiming to minimize jitter at
high speeds. To incorporate this function, LATCH should be connected to V
CC
. If this function is unused,
CLK+ should be connected to V
CC
, CLK- should be left unconnected, and LATCH should be connected to
GND.
Short-Circuit Protection
If BIASMAX or MODSET are shorted to ground, the output modulation and bias currents will be turned
off.
G52350-0, Rev 3.2
02/26/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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