PHYSICAL LAYER PRODUCT
ETHERNET PRODUCT
VSC7321
VSC7321 Meigs-II
™
- 10 x 1G and 10G Ethernet MAC Chip
S P E C I F I C AT I O N S :
Implemented in low Power 0.18 micron CMOS Technology, 2.5V/3.3V IO
Industrial Temperature Range (-40ºC to +85ºC)
Standard 5-Pin P1149.1 JTAG Test Port
Packaged in a 728 pin TBGA
A P P L I C AT I O N S :
Enterprise and Metro Ethernet Switches
Multi-Service Provisioning Platforms
F E AT U R E S :
Ten Triple-Speed Ethernet MACs w/Support for RGMII/GMII/MII
Integrated GbE SERDES for Direct Connection to Optical Modules
Intelligent VLAN and MPLS Identification
Loss less flow Control in Metro Applications up to 10km
10GbE MAC w/Integrated XAUI SERDES Interface Compliant
to IEEE 802.3ae
Low Pin Count, low Power OIF SPI-4.2 System Interface
PHY
Metro SONET/SDH Transport (ADMs)
Edge and Core Aggregation Routers
DWDM Transport Terminals (Wavelength Routers)
A P P L I C AT I O N D I A G R A M S :
10 x GbE MAC interfacing to NPU or ASIC
10 x GbE MAC w/
RGMII/GMII
PHY
VSC7321
NPU or
ASIC
Switch or
Transceiver
Extensive Loopback Capabilities for Both Line and System Side
RGMII/GMII
SPI-4.2
Backplane or
Switch Interface
Configurable Parallel or Serial CPU Interface
10 x GbE over SONET/SDH using the VSC9118
Dual MIIM Interface for Managing PHY Devices
Independent Egress and Ingress Shaping/Policing
Rate Limiting in 1 Mb/s Increments
802.3ad Compliant Link Aggregation and Trunking
Statistical Support for RMON 1 (RFC2819), IEEE 802.3 Annex
30A, and SNMP (RFC 1213, 1573, and 1643)
Supports Both Minimum Size 64B Frames as well as 9600B
Jumbo Frames
Automatic Generation of PAUSE Frames Based on Programmable
Per Port FIFO Watermarks
O/E
O/E
O/E
10 x GbE MAC w/
Integrated Serdes
Packet Mapper
with VC and GFP
STS-1
Grooming TSI
VSC7321
VSC9118
VSC9185
Serial
SPI-4.2
Backplane
Interface
10 GbE MAC interfacing to NPU or ASIC
10 GbE MAC w/
Integrated XAUI
VSC7321
NPU or
ASIC
SPI-4.2
Switch or
Transceiver
XAUI
Backplane or
Switch Interface
PB-VSC7321-002
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
