VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Multi-Gigabit Interconnect Chip
The VSC7217 presents recovered data on
Rn(7:0)
and status on
IDLEn, KCHn
and
ERRn.
These outputs
are timed either to each channel’s own recovered clock (RCLKn/RCLKNn), to Channel A’s recovered clock
(RCLKA/RCLKNA), or to
REFCLK.
The output timing reference is selected by
RMODE(1:0)
(see Table 5).
The transmitter input skew buffer error outputs
TBERRn
and the analog signal detect outputs
PSDETn
and
RSDETn
are also synchronized to the selected output timing reference. There are two choices for
REFCLK-
based timing, which differ in the positioning of the data valid window associated with the output signals timed
to
REFCLK.
When
RMODE(1:0)=00, REFCLK
is approximately centered in the output data valid window
as in the VSC7214. When
RMODE(1:0)=01, REFCLK
slightly leads the data valid window so that output
data appears to have a more typical “Clock-to-Q” timing relationship to
REFCLK.
Table 5: Receive Interface Output Timing Mode
RMODE(1:0)
00
01
1 0
1 1
Output Timing Reference
REFCLK (Centered)
REFCLK (Leading)
RCLKA/RCLKNA
RCLKn/RCLKNn
The term “word clock” is used for whichever clock
(
REFCLK, RCLKA/RCLKNA
or
RCLKn/
RCLKNn)
is selected as the output timing reference. If
RMODE(1)
is HIGH, each channels’
RCLKn/
RCLKNn
outputs are complementary outputs at 1/10th or 1/20th the baud rate of the incoming data depending
upon
DUAL.
When
RCLKA/RCLKNA
is selected as the output timing reference, Channel B, C and D
RCLKn/RCLKNn
outputs are copies of
RCLKA/RCLKNA.
If
RMODE(1)
is LOW, each channels’
RCLKn/RCLKNn
outputs are held in a LOW/HIGH state, respectively, and the data and status outputs are
timed to
REFCLK.
If
DUAL
is HIGH, all data at the four output ports are synchronously clocked out on both
positive and negative edges of the selected word clock at 1/20th the baud rate. If
DUAL
is LOW, the data is
clocked out of the VSC7217 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing
waveforms for the output data and status are shown in Figure 6, Figure 7 and Figure 8.
Figure 6: Receive Timing,
RMODE(1:0)
= 00
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Rn(7:0)
IDLEn
KCHn
ERRn
Valid
Valid
Valid
G52325-0, Rev. 3.0
6/14/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
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