VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Multi-Gigabit Interconnect Chip
Multi-Gigabit Interconnect Chip
VSCV7S2C1672-0116
The term “word clock” will be used for whichever clock, REFCLK, RCLKA/RCLKNA or RCLKn/
RCLKNn, is selected as the output timing reference. If RMODE(1) is HIGH, each channels’ RCLKn/RCLKNn
outputs are complementary outputs at 1/10th or 1/20th the baud rate of the incoming data depending upon
DUAL. When RCLKA/RCLKNA is selected as the output timing reference, the Channel B, C and D RCLKn/
RCLKNn outputs are copies of RCLKA/RCLKNA. If RMODE(1) is LOW, then each channels’ RCLKn/
RCLKNn outputs are held in a LOW/HIGH state, respectively, and the data and status outputs are timed to
REFCLK. If DUAL is HIGH, all data at the four output ports are synchronously clocked out on both positive
and negative edges of the selected word clock at 1/20th the baud rate. If DUAL is LOW, the data is clocked out
of the VSC7216-01 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing
waveforms for the output data and status are shown in Figure 6, Figure 7 and Figure 8.
Figure 6: Receive Timing, RMODE(1:0) = 00
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Rn(7:0)
IDLEn
KCHn
ERRn
Valid
Valid
Valid
Figure 7: Receive Timing, RMODE(1:0) = 01
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Rn(7:0)
IDLEn
KCHn
ERRn
Valid
Valid
Valid
Figure 8: Receive Timing, RMODE(1:0) = 1X
RCLKn
(DUAL = 0)
RCLKn
(DUAL = 1)
Rn(7:0)
IDLEn
KCHn
ERRn
Valid
Valid
Valid
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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 10
G52352-0, Rev 3.2
05/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
