VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7146
2.5Gb/s, 20-Bit Transceiver
Deserializer
The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7146 provides
a TTL recovered clock, RBC, at one twentieth of the serial baud rate. The clock is generated by dividing down
the high-speed clock which is phase-locked to the serial data. The serial data is retimed by the internal high-
speed clock, and deserialized. The resulting parallel data will be captured by the adjoining protocol logic on the
rising edge of RBC.
If serial input data is not present, or does not meet the required baud rate, the VSC7146 will continue to
produce a recovered clock and RBC will automatically lock to the REF reference clock. This eliminates the
need for a Lock-to-Reference input pin and simplifies the support software for that function.
Word Alignment
The VSC7146 provides 7-bit Fibre Channel “comma” character recognition and data word alignment. Word
synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7146
constantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is
“0011111XXX”, where the leading zero corresponds to the first bit received. The “comma” sequence is not
contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within
special characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in
Fibre Channel systems. Improper alignment of the “comma” character is defined as either of the following
conditions:
1) The “comma” is not aligned within the 10-bit transmission character such that T0...T6 = “0011111.”
2) The “comma” straddles the boundary between two 10-bit transmission characters.
When EN_CDET is HIGH and an improperly aligned “comma” is encountered, the internal data is shifted
in such a manner that the “comma” character is aligned properly in R[0:6] as shown in Figure 1. This results in
proper character and word alignment. When the parallel data alignment changes in response to a improperly
aligned “comma” pattern, some data which would have been presented on the parallel output port may be lost.
However, the synchronization character and subsequent data will be output correctly and properly aligned.
When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data
pattern.
On encountering a “comma” character, COM_DET is driven HIGH to inform the user that realignment of
the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the “comma”
character and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the
adjoining protocol logic on the rising edge of RBC. Functional waveforms for synchronization are shown in
Figure 2 and Figure 3. Figure 2 shows the case when a “comma” character is detected and no phase adjustment
is necessary. It illustrates the position of the COM_DET pulse in relation to the “comma” character on R[0:6].
Figure 3 shows the case where the K28.5 is detected, but it is out-of-phase and a change in the output data
alignment is required. Note that up to three characters prior to the “comma” character may be corrupted by the
realignment process.
G52162-0, Rev. 2.7
8/28/00
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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