VSC7145
Datasheet
Receive Bus Operation
Case A: Receive Bus Operation (RXRATE = LOW, RBCSYNC = LOW)
When RXRATE is LOW and RBCSYNC is LOW, the deserializer runs at half speed (1.06Gb/s or 1.25Gb/s). The
th
RBC0/RBC1 clocks run at 1/20 of the baud rate (53.125MHz or 62.5MHz), and the rising edges of RBC0 and
RBC1 are located in the middle of the R[0:9] valid period. This mode is the normal mode for half-speed operation
and is compatible with the 10-bit interface specification for Fibre Channel and Gigabit Ethernet.
If ENCDET is HIGH, the RBC clocks will be stretched up to 19 bits in order to align incoming serial data with the
parallel bus as indicated by the K28.5 detector. COMDET will always be centered on the rising edge of RBC1.
RBC0
RBC1
t
t
2
t
t
2
1
1
Data Valid
Data Valid
Data Valid
R[0:9]
COMDET
Figure 4. Receive Timing Waveforms (RXRATE = 0, RBCSYNC = 0)
Table 9. Receive AC Characteristics (RXRATE = 0, RBCSYNC = 0)
Symbol
Parameter
Min
3.0
3.0
2.0
2.0
Typ
3.9
4.5
3.5
4.5
Max
Units
ns
Condition
t1
R[0:9], COMDET valid prior to RBC0/RBC1
rising edge
1.25Gb/s operation.
1.06Gb/s operation.
1.25Gb/s operation.
1.06Gb/s operation.
bc = bit clock.
ns
t2
R[0:9], COMDET valid after RBC0 or RBC1
rising edge
ns
ns
RLAT
Latency from Rx to R[0:9]
40bc +
5ns
bc
ns
10 of 22
G52213 Revision 4.3
October 24, 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
