VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7139
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Figure 4: Receive Timing Waveforms
RCx0
RCM=LOW
RCx1
RCx0
RCM=HIGH
RCx1
T
1
T
2
VALID
VALID
Rx(0:9)
SYNCx
VALID
+/-Rx
Rx0
Rx1
Rx2
R
LAT
RCx1
Table 4: Receive AC Characteristics
Parameters
T
1
Description
TTL Outputs Valid prior to RCx1/
RCx0 rise
TTL Outputs Valid after RCx1 or
RCx0 rise
Delay between rising edge of RCx1
to rising edge of RCx0
Period of RCx1 and RCx0
TTL Output rise and fall time
Latency from serial bit Rx0 to rising
edge RCx1
Data acquisition lock time
(1)
Min
4.0
3.0
TBD
3.0
2.0
TBD
10 x T
RX
-500
1.98 x
T
REF
—
12bc +
2.77ns
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
10 x T
RX
+500
2.02 x
T
REF
2.4
13bc +
7.28ns
1400
Units
ns
Conditions
@ 1.0625Gb/s
@ 1.25Gb/s
@ 1.36Gb/s
@ 1.0625Gb/s
@ 1.25Gb/s
@ 1.36Gb/s
T
RX
is the bit period of the
incoming data on Rx.
Whether or not locked to
serial data.
Between V
IL(max)
and
V
IH(min)
, into 10 pf. load.
bc = Bit clock
ns = Nano second
T
2
T
3
T
4
T
R
, T
F
R
LAT
T
LOCK
ns
ps
ps
ns
bit
times
8B/10B IDLE pattern.
Tested on a sample basis
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH, rev. 4.3.
G52196-0, Rev 3.3
5/14/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 7
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