VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
Figure 5: Receive Timing Waveforms
T
4
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
RCLK
T
3
RCLKN
T
1
T
2
Data Valid
R(0:9)
Data Valid
Data Valid
Table 3: Receive AC Characteristics
Parameters
T
1
T
2
T
3
T
4
T
R
, T
F
R
LAT
T
LOCK
*
Description
TTL Outputs Valid prior
to RCLK/RCLKN rise
TTL Outputs Valid after
RCLK or RCLKN rise
Delay between rising
edge of RCLK to rising
edge of RCLKN
Period of RCLK and
RCLKN
R(0:9), COMDET,
SIGDET, RCLK and
RCLKN rise and fall time
Latency from RX to
R(0:9)
Data acquisition lock time
Min.
4.0
3.0
3.0
2.0
10 x T
RX
-500
1.98 x
T
REFCLK
—
Max.
—
—
—
—
10 x T
RX
+500
2.02 x
T
REFCLK
2.4
Units
ns
ns
Conditions
@ 1.0625Gb/s
@ 1.25Gb/s
@ 1.0625Gb/s
@ 1.25Gb/s
T
RX
is the bit period of the
incoming data on Rx.
Whether or not locked to
serial data.
Between V
IL(MAX)
and
V
IH(MIN)
, into 10 pf. load.
bc = Bit clock
ns = Nano second
8B/10B IDLE pattern.
bc= bit clocks
ps
ps
ns
bc
ns
bc
12 bc + 1 ns
—
13 bc + 9 ns
1400
* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3
G52187-0 Rev. 2.4
1/17/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
