VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Functionality
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Device Configurations
Four devices are specified in this datasheet: VSC7127R, VSC7127T, VSC7129R and VSC7129T. The
VSC7127 is pin-compatible to the HDMP-0451. The VSC7129 is pin compatible with the HDMP-0452. The
VSC712xR is configured as a Repeater when pin 12, MODE, is LOW, or a Retimer when HIGH. The
VSC712xT is configured as a Retimer when pin 12, MODE, is LOW, or a Repeater when HIGH.
Port Bypass Circuits
The VSC712x contains six Port Bypass Circuits (PBCs) which are 2-to-1 multiplexers used to steer serial
signals. Each PBC, PBCx has a single select line, SELx, which when HIGH, selects the external input, Ix, to
PBCx and when LOW, selects the output of the previous PBC. PCB5 does not have an external input but selects
between the output of the CRU (when SEL5 is HIGH) and the output of PBC0 (when SEL5 is LOW). These
controls allow FC-AL loops to include a functional device on the loop or exclude a non-functional device from
the loop.
FibreTimer
™
Clock Recovery Unit—Repeater Mode
The Clock Recovery Unit (CRU) is a digital PLL which extracts the clock from the incoming data and sam-
ples the data with the extracted clock. In repeater mode, the output of the CRU is synchronized to the recovered
clock and has improved signal quality due to amplification of the signal and attenuation of jitter. Latency
through the device is quite low, just a few bit times. Multiple repeaters can be cascaded without accumulation
of jitter. MODE determines whether the CRU is a Repeater or a Retimer.
FibreTimer
™
Clock Recovery Unit —Retimer Mode
MODE may configure the CRU as a retimer where the recovered data is placed into an elasticity buffer.
Data is taken out of the elasticity buffer and retransmitted synchronously to the local REFCLK. For Fibre Chan-
nel data, Fill words will be added and dropped in the elasticity buffer in order to accomodate the differences in
speed between the incoming data and the REFCLK. The retimer does not transfer jitter from the input to the
output but has longer latency, up to 4 word times, through the device.
FibreTimer
™
Clock Recovery Unit—Bypass Mode
When SEL5 is LOW, PBC5 selects the output of PBC0 and the CRU is unused. In this mode, the CRU is
powered down to reduce power dissipation. If the part will be used only in this mode, REFCLK and MODE are
ignored and can be left open. If the CRU is bypassed, the Signal Detect Unit is disabled and the output is LOW.
Signal Detection
A signal detect unit (SDU) monitors IO+/- and the output of the CRU to determine if there is a valid Fibre
Channel signal present. The SIGDET is updated every 160 bits (an “interval”) with the previous interval’s status
of three different Signal Detect Units: analog signal amplitude (ASDU), run length check (RLLSDU), Ordered
Set density (OSSDU). If the input amplitude is less than 200mV (differential), ASDU will be set LOW. If the
input amplitude is greater than 400mV, ASDU will be asserted HIGH. If a run length violation occurs (more
than 5 consecutive ones or zeros), the RLLSDU will be set LOW and stay LOW until the occurrence of a valid
G52298-0, Rev 4.3
05/01/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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