EL
V
O
ITY
C
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Figure 4: Transmit Timing Waveforms
Data Sheet
VSC7123
REFCLK
T
1
T
2
T(0:9)
Data Valid
Data Valid
Data Valid
Table 2: Transmit AC Characteristics
Parameters
T
1
T
2
T
SDR
,T
SDF
T
LAT
Description
T(0:9) Setup time to the rising
edge of REFCLK
T(0:9) hold time after the rising
edge of REFCLK
TX+/TX- rise and fall time
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX-
Min
1.5
1.0
—
8bc
Typ
—
—
—
—
Max
—
—
300
8bc+
4ns
Units
ns
ns
ps
ns
Conditions
Measured between the valid data
level of T(0:9) to the 1.4V point
of REFCLK.
20% to 80%, 50Ω load to
V
DD
-2.0.
bc = Bit clocks
ns = Nano second
Transmitter Output Jitter Allocation
RJ
DJ
Random jitter (RMS)
Serial data output deterministic
jitter (pk-pk)
—
—
5
30
8
80
ps.
ps.
Measured at SO+/-, 1 sigma
deviation of 50% crossing point.
IEEE 802.3Z Clause 38.68,
tested on a sample basis.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52212-0, Rev 4.3
03/25/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
