VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Input Structures
Two input structures exist in this part; TTL and High Speed, Differential Inputs. The TTL Inputs will inter-
face with any TTL or 3.3V or 5V CMOS outputs. The High Speed, Differential Inputs are intended to be AC
Coupled per the FC-PH specification. Being AC Coupled, the High Speed, Differential Input buffers are biased
at V
DD
/2. Refer to Figure 3 for High Speed, Differential Input structure.
Figure 3: High Speed, Differential Inputs (L_SIn/IN)
VDD
3.3K
+3.3 V
INPUT+
3.3K
VDD/2
3.3K
INPUT-
3.3K
GND
0V
Because the VSC7122 output buffers are PECL outputs referenced to V
DD
, the High Speed Differential out-
puts may not be direct coupled to the high speed differential inputs. One example of how to differentially cas-
cade the two VSC7122 is shown in Figure 4.
Figure 4: Cascading Two VSC7122
V
DD
VSC7122
191
191
.01
VSC7122
OUT+
OUT -
124
124
.01
IN+
IN -
75 Ohm Board/Termination Example
Page 6
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
