VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Table 2: AC Characteristics
(Over recommended operating conditions).
Parameters
T
1
T
2
T
SDR
, T
SDF
Description
Flow-Through Propagation Delay
Rising Edge to Rising Edge
Flow through Propagation Delay
Falling Edge to Falling Edge
Serial data rise and fall time
Min.
Max.
7.0
7.0
Units
ns
ns
ps.
Conditions
Delay with all circuits bypassed. 75
Ohm Load
Delay with all circuits bypassed. 75
Ohm load.
20% to 80%, tested on a sample basis
—
300
Table 3: DC Characteristics
(Over recommended operating conditions).
Parameters
Description
Min
Typ
Max
Units
Conditions
V
IH(TTL)
V
IL(TTL)
I
IH(TTL)
I
IL(TTL)
V
DD
I
DD
P
D
∆
V
IN
∆
V
OUT50
∆
V
OUT75
Input HIGH voltage (SEL - TTL)
Input LOW voltage (SEL - TTL)
Input HIGH current (SEL- TTL)
Input LOW current (SEL - TTL)
Supply voltage
Supply current
Power Dissipation
Receiver differential peak-to-peak
Input Sensitivity, IN+/- & L_SIn+/-
Output differential peak-to-peak
voltage swing
Output differential peak-to-peak
voltage swing
2.0
0
—
—
3.10
—
—
—
50
—
—
—
0.35
5.5
0.8
500
-500
3.50
150
0.5
2600
V
V
µ
A
µ
A
V
mA
W
mVp-p
mVp-p
mVp-p
I
IH
< 6.6 mA @ V
IH
= 5.5 V
—
V
IN
= 2.4 V
V
IN
= 0.5 V
V
DD
= 3.30V + 5%
Outputs open, V
DD
= V
DD
max
Outputs open, V
DD
= V
DD
max
AC Coupled.
Internally biased at V
DD
/2
50
Ω
to V
DD
– 2.0 V
75
Ω
to V
DD
– 2.0 V
300
1000
1200
—
2200
2200
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
