VSC7104
Datasheet
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using a
four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information, see
the JEDEC standard.
Table 13. Thermal Resistances
θ
0
JA (°C/W) vs. Airflow (ft/min)
Part Number
VSC7104VP
VSC7104XVP
VSC7104SX
VSC7104XSX
θJC
0.5
0.5
0.5
0.5
100
29
200
32
32
32
32
27
27
27
27
29
29
29
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described
in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the
following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment
Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
Moisture Sensitivity
This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
12 of 14
VMDS-10059 Revision 4.2
February 27, 2007
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
