VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC6424
Figure 1: Synchronized VSC6424 Block Diagram
40
VSC6424
SLDN/SYNC
CLKT
500 Mb/s Video
Shift Register IC
120
40
VSC6424
SLDN/SYNC
3 - 30
VSC6424
40
SLDN/SYNC
Synchronization
Several VSC6424 chips can be synchronized together while in internal timing mode by connecting the slow
speed TTL clock output (CLKT) of a master chip to the synchronization input (SYNC) of a slave chip. The inter-
nal timing generator synchronizes to the rising edge of the SYNC input. Given that (n) is the number of high
speed clock cycles for a given modulus mode, synchronization takes two times (n) or (2n) clock cycles to lock
in. If it is necessary to synchronize more than two VSC6424 devices use the TTL clock output (CLKT) from
one chip to drive the SYNC inputs of each of the slave devices. See Figure 2 for a block diagram. See Figure 7
for a timing illustration of the synchronization timing of the slave chip. See Table 5 to determine (n) for a
selected modulus.
In MUX mode multiple VSC6424 chips can also be synchronized by providing a slow speed clock to the
SYNC input on all of the devices. This slow speed clock must be synchronized with high speed clock and based
on the modulus that the MUX is set to. For example if the VSC6424 is set to 8:1 mode and the high speed clock
is set to 400MHz then the SYNC input must be 50MHz.
MPU Address Interface
An
Address Interface
mode translates TTL compatible addresses to ECL compatible output levels. This is
provided for compatibility with the Bt424. When the Address Enable (AEN) signal is low, data from the
Address Line
A<0:4>
TTL input pins is transferred to the
DOUT<0,2,4,6,7>
ECL output pins with one clock
cycle delay. When
AEN
is high, the
A<0:4>
inputs are ignored. The
DOUT<0:7>
data is always synchronized
to
CLK,
regardless of the state of
AEN.
See Figure 9 for a timing illustration of this function.
Video Blanking
The VSC6424 also has a blanking function for video applications. In multiplexer mode, this function allows
zeroing of the high speed outputs (DOUT<0:7>). Setting
HBLANK
or
VBLANK
low drives all
DOUT<0:7>
outputs low synchronously with the clock (CLK). The outputs will be driven low on the modulus boundary. The
outputs are driven low for (n) clock cycles given that (n) is the modulus mode that the chip is set to. See table 4
to determine the value of (n) for a given modulus.
G52236-0, Rev 3.0
7/13/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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