VITESSE
SEMICONDUCTOR CORPORATION
1Gb/s 16-Channel
Drive-Side Deskew IC
Figure 5: CAL Mode: Pre-Calibration Delay Range
Data Sheet
VSC6250
32 Coarse Vernier Steps +
64 Fine Vernier Steps
(1)
Delay
~275ps Fine Vernier Range
000
Delay[0:10]
Figure 6: CAL Mode: Post-Calibration Delay Range
32 Coarse Vernier Steps +
64 Fine Vernier Steps
(1)
Delay
= Unused Codes
000
Delay[0:10]
NOTE: (1) There are 32 coarse vernier codes and 64 fine vernier codes. Not all of the codes are used to reach
maximum delay. The current design utilizes 22 coarse codes and 47 fine vernier codes. Future designs will utilize 22
course designs and 59 fine vernier codes. These numbers must be used when calculating INL and DNL. System cal-
ibration should be performed with the maximum usable codes. When a code is programmed beyond the maximum
utilized code, the delay will toggle between maximum delay and maximum delay minus 1LSB. Please contact your
local Vitesse sales representative to determine when the future design will be available.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52197-0, Rev. 4.0
8/19/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
