VSC6134
Datasheet
The read and write pointers of the clock crossing FIFO are reset to their initial states on device reset and
after every new frame alignment. However, the pointers increment normally during the out of frame
condition.
Upon reset, the RAM contents are forced to a known value by writing them to all zeros.
The clock crossing block I/O is shown in the following table.
Table 17. Clock Crossing Block I/O Description
Name
Direction
Function
MPU Clock Domain
global_mode
IN
FIFO mode (formerly global mode) selects the received data and control
signals. See “Global MPU Register 6 - Global Configuration Control 1,”
page 368.
ptr_reset
IN
IN
Pointer reset initializes the clock-crossing FIFO pointers and causes a
subsequent NFA. See “Global MPU Register 6 - Global Configuration
Control 1,” page 368.
add_stuff_dis
Stuff disable puts the block into the legacy RS FEC frame of 12.24 us
without the 16 bytes of stuff in each OTUk row. See “Global MPU Register
6 - Global Configuration Control 1,” page 368.
add_async
IN
IN
Add asynchronous mode (add side only). See “Global MPU Register 6 -
Global Configuration Control 1,” page 368.
fec_enc_bypass
Add FEC encoder bypass (add side only) is for SONET/SDH pass through
applications. See “Global MPU Register 6 - Global Configuration Control
1,” page 368.
mpu_wrena
ae_glb_sel
uthresh
IN
IN
IN
MPU write enable.
MPU address decode and select for the block.
Upper threshold value for add-path asynchronous mapping. (Add side
only.) See “Global MPU Register 6 - Global Configuration Control 1,”
page 368.
lthresh
IN
IN
Lower threshold value for add-path asynchronous mapping. (Add side
only.) See “Global MPU Register 6 - Global Configuration Control 1,”
page 368
hystcount
Hysteresis value for add-path asynchronous mapping. (Add side only.)
See “Global MPU Register 6 - Global Configuration Control 1,” page 368.
mpu_clk
IN
IN
MPU clock.
mpu_resetn
MPU reset.
Receive Clock Domain
Receive clock domain reset.
Receive clock.
rx_resetn
rx_clk
IN
IN
nfa_in
IN
New frame alignment.
Drop clock enable for line receive to line transmit loopback.
Data in.
drop_clken
datain
IN
IN
init_done
OUT
Memory initialization done.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
