VSC6134
Datasheet
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In the Intel Synchronous Mode – Read Cycle section, the row for the Hold time for csn
assert/de-asserted to mpu_clk rise parameter was removed. The delay for mpu_clk rise to rdyrcvn
de-asserted parameter was changed from 8 ns to 16 ns, and the delay for mpu_clk rise to rdyrcvn
asserted parameter was changed from 8 ns to 16 ns. For more information, see Table 446, page 401.
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In the Intel Synchronous Mode – Write Cycle section, the row for the Hold time for csn
assert/de-asserted to mpu_clk rise parameter was removed. The delay for mpu_clk rise to rdyrcvn
de-asserted parameter was changed from 8 ns to 16 ns, and the delay for mpu_clk rise to rdyrcvn
asserted parameter was changed from 8 ns to 16 ns. For more information, see Table 447, page 402.
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In the Intel Asynchronous Mode – Read Cycle section, the figure and notes were updated. For more
information, see Figure 68, page 188 and Figure 90, page 403.
In the Intel Asynchronous Mode – Write Cycle section, the figure and notes were updated. For
more information, see Figure 70, page 190 and Figure 91, page 404.
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PWM (pulse width modulation) was removed.
RLL implementation option B was removed, because it is no longer supported. The RLL
implementation option A was renamed to RLL implementation. For more information about RLL
implementation, see “Rate Locked Loop (RLL) Controller,” page 115.
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In the DC characteristics for LVTTL, the entire table for LVTTL characteristics was updated. For
more information, see Table 430, page 389. In addition, the 3.3 V LVTTL minimum DC currents at
rated voltages table and the 3.3 V LVTTL receiver input leakage current specifications were
removed.
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In the DC characteristics for the 3.3 V LVTTL driver slew rate, the 50 Ω reference was removed
from the table title and introductory text. The footnote regarding how output PAD rise and fall
times are measured from “…between 20% and 80% of “V
” to “…between 20% and 80% of
TVDDH
V
and V
” was revised. For more information, see Table 431, page 389.
DDIOTTL1
DDIOTTL2.
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In the DC characteristics for the LVDS receiver, the entire table for the LVDS receiver and the table
for the LVDS driver was updated. For more information, see Table 432, page 390 and Table 433,
page 390.
In the AC characteristics for the Digital Wrapper Receive Interface (Overhead Extract) section, the
following tables were removed to eliminate redundant information:
Receive Interface (CBR 10 G <-> Legacy FEC Mode)
Receive Interface (10 GbE <-> FEC Mode)
Receive Interface (10 GbE <-> Legacy FEC Mode)
Transmit Interface (CBR 10 G <-> Legacy FEC Mode)
Transmit Interface (10 GbE <-> FEC Mode)
Transmit Interface (10 GbE <-> Legacy FEC Mode)
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In the AC characteristics for the Digital Wrapper Receive Interface (Overhead Extract) section, the
Serial Interface Receive Data Timing diagram was updated. For more information, see Figure 80,
page 393.
In the AC characteristics for the Digital Wrapper Receive Interface (Overhead Extract) section, the
table title from the Receive Interface (CBR 10 G <-> FEC Mode) was changed to Receive
Interface. The maximum values were modified for the delay from rising clock edge (T
) and
DFSO
delay from rising clock edge (T
page 393.
) from 6 ns to 9 ns. For more information, see Table 437,
DDO
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In the AC characteristics for the Digital Wrapper Receive Interface (Overhead Extract) section, the
table title was changed from Transmit Interface (CBR 10 G <-> FEC Mode) to Transmit Interface.
The parameter name from hold time (T
) was changed to hold time after rising clock edge
HFSI
(T
). The parameter name from hold time (T ) was changed to hold time after rising clock
HDI
HFSI
28 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
