VSC6134
Datasheet
Table 73. Global Registers (continued)
Address
0x01D
0x01E
0x01F
0x020
0x021
Register Name
Reference
Global MPU Register 29 - Add PFD TX Clock Ratio Register
Global MPU Register 30 - Drop PFD RX Clock Ratio Register
Global MPU Register 31 - Drop PFD TX Clock Ratio Register
Global MPU Register 32 - SONET Block Interrupts
See Section 3.13.26, page 384.
See Section 3.13.27, page 384.
See Section 3.13.28, page 385.
See Section 3.13.29, page 385.
See Section 3.13.30, page 386.
Global MPU Register 33 - Global Client Interface
Configuration Register 0
0x022
0x023
Global MPU Register 34 - Global Client Interface
Configuration Register 1
See Section 3.13.31, page 386.
See Section 3.13.32, page 387.
Global MPU Register 35 - Block Interrupt Mask
Table 74. Frame Aligner Registers
Address
0x100
0x101
0x102
0x103
0x104
Register Name
Reference
Drop FEC Frame Aligner Register 0
Drop FEC Frame Aligner Configuration 1
Drop FEC Frame Aligner Configuration 2
Drop FEC Frame Aligner Configuration 3
Drop FEC Frame Aligner Status
See Section 3.10.6, page 355.
See Section 3.10.7, page 355.
See Section 3.10.8, page 356.
See Section 3.10.9, page 356.
See Section 3.10.10, page 357.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
