VSC6134
Datasheet
3.3.12
BER Monitor Signal Fail Error Threshold (MSW) Register
Address:
0xC6A: Add Path
0x46A: Drop Path
0x0001
Register Reset Value:
Table 121. BER Monitor Signal Fail Error Threshold Register (MSW) Register
Reset
Value
Bit
15:3
2:0
Name
Access
RO
Description
Reserved
0x000
0x1
SF_ERR_THRESH[18:16]
R/W
Upper portion of the SF_ERR_THRESH register
3.3.13
BER Monitor Signal Fail Error Threshold (LSW) Register
Address:
0xC6B: Add Path
0x46B: Drop Path
0x3396
Register Reset Value:
Table 122. BER Monitor Signal Fail Error Threshold (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
SF_ERR_THRESH[15:0]
R/W
Lower portion of the SF_ERR_THRESH register
0x3396
3.3.14
BER Monitor Signal Fail Clear Threshold (MSW) Register
Address:
0xC6C: Add Path
0x46C: Drop Path
0x0000
Register Reset Value:
Table 123. BER Monitor Signal Fail Clear Threshold (MSW) Register
Reset
Value
Bit
15:3
2:0
Name
Access
RO
Description
Reserved
0x000
0x0
SF_CLR_THRESH[18:16]
R/W
Upper portion of the SF_CLR_THRESH register.
237 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
