VSC6134
Datasheet
Table 98. LOHM Configuration Register (continued)
Reset
Value
Bit
13
Name
Access
Description
APSDIR
R/W
Defines the valid APS direction mode of equipment (bits
0
[2:0] in K2 byte).
1: If the provisioned mode is unidirectional (100 of K2 byte
[2:0]).
0: If the provisioned mode is bidirectional (101 of K2 byte
[2:0]) (default).
12
S1COMP_MODE
R/W
Defines the compare mode for S1 byte validation.
1: Validation is performed based on the whole S1 byte [7:0].
0: Validation is performed based on the lower nibble of the
S1 byte [3:0] (default).
0
11
10
Reserved
RO
0
0
M0_MODE
R/W
Defines the mode for M0, M1 byte monitor.
1: Only M1 byte is monitored.
0: M0 and M1 bytes are monitored (default).
9:0
Reserved
RO
0x000
3.2.3
LOHM Interrupt Mask Register
Address:
0xDED: Add Path
0x5ED: Drop Path
0xFFE0
Register Reset Value:
Table 99. LOHM Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
B2ERR_M
R/W
Mask for B2 BIP-8 Error interrupt status bit
1: Mask interrupt
0: Allow B2ERR_S to generate the interrupt
1
1
1
1
1
1
14
13
12
11
10
K1K2NEW_M
K1INC_M
AIS_M
R/W
R/W
R/W
R/W
R/W
Mask for new K1K2 interrupt status bit
1: Mask interrupt
0: Allow K1K2NEW_S to generate the interrupt
Mask for K1 inconsistency error interrupt status bit
1: Mask interrupt
0: Allow K1INC_S to generate the interrupt
Mask for AIS_S alarm interrupt status bit
1: Mask interrupt
0: Allow AIS_S to generate the interrupt
RDI_M
Mask for RDI_S alarm interrupt status bit
1: Mask interrupt;
0: Allow RDI_S to generate the interrupt
APSMM_M
Mask for APS mode mismatch interrupt status bit
1: Mask interrupt
0: Allow APSMM_S generate the interrupt
227 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
