VITESSE
Data Sheet
VS8004/8005
2.5 Gbits/sec 4-Bit Multiplexer/
Demultiplexer Chipset
VS8005 AC Characteristics
(Over recommended operating conditions)
Parameter
t
CLK
t
CAD
t
PWH
t
PWL
t
TLH
,t
THL
Description
High Speed clock period (CLK, NCLK)
CLK4, NCLK4 to D(
0
:3), ND(
0
:3)
SKIP, NSKIP pulse with (HIGH)
SKIP, NSKIP pulse with (LOW)
ECL output transition time (LOW to HIGH & HIGH to
LOW) for D(0:3), ND(0:3) and CLK4, NCLK4 (Driving
50
Ω
)
SDATA, NSDATA phase timing margin with respect to
t
SU
+
t
H
CLK, NCLK input:
Phase Margin =
1 – -------------------
360°
-
t
C
where
t
c
is minimum clock cycle.
Min
400
-
2
2
-
Typ
-
400
-
-
500
Max
-
-
-
-
-
Units
ps
ps
ns
ns
ps
Phase
Margin
135
_
-
degrees
Figure 4: VS8005 Waveforms
t
CLK
CLK , NCLK
(1)
SDATA, NSDATA
CLK4 , NCLK4
(1)
D
Ø
D
1
D
2
D
3
t
TLH,
t
THL
t
TLH,
t
THL
t
C4D
D(0:3), ND(0:3)
VALID DATA
t
PWH
SKIP, NSKIP
(1) Rising edge causes serial data to be latched.
t
PWL
G52012-0 Rev. 2.0
®
VITESSE
Semiconductor Corporation
Page 5
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