IRFP264, SiHFP264
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
•
Low stray inductance
•
Ground plane
•
Low leakage inductance
current transformer
-
+
-
+
-
R
G
•
•
•
•
dV/dt controlled
by
R
G
Driver same type as D.U.T.
I
SD
controlled
by
duty factor "D"
D.U.T. - device
under
test
+
-
V
DD
Driver gate drive
P.W.
Period
D=
P.W.
Period
V
GS
= 10
V*
D.U.T. I
SD
waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T.
V
DS
waveform
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Inductor current
Body diode forward drop
Ripple
≤
5
%
I
SD
*
V
GS
= 5
V
for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91217.
Document Number: 91217
S-81264-Rev. A, 21-Jul-08
www.vishay.com
7
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