DG9424, DG9425, DG9426
Vishay Siliconix
SCHEMATIC DIAGRAM
Typical Channel
V+
V
L
S
V
IN
Level
Shift/
Drive
D
GND
V-
Figure 1.
TEST CIRCUITS
V
L
V+
Logic
Input
V
INH
50 %
V
INL
V
L
V
IN
NO or NC
IN
GND
V-
R
L
300
Ω
C
L
35 pF
Switch
Output
Switch
V+
COM
V
OUT
V
OUT
0V
t
ON
90 %
0.9 x V
OUT
t
OFF
t
r
< 5 ns
t
f
< 5 ns
V-
C
L
(includes fixture and stray capacitance)
V
OUT
= V
IN
R
L
R
L
+ r
ON
Note:
Logic input waveform is inverted for switches that
have the opposite logic sense control
Figure 2. Switching Time
V
L
V+
Logic
Input
3V
50 %
0V
V
IN1
V
O1
Switch
Output
0V
V
IN2
V
O2
0V
V
IN1
V
IN2
NO
1
IN
1
NC
2
IN
2
GND
COM
1
COM
2
V
O2
V
O1
90 %
R
L1
300
Ω
V-
R
L2
300
Ω
C
L2
35 pF
C
L1
35 pF
Switch
Output
90 %
t
D
t
D
V-
C
L
(includes fixture and stray capacitance)
Figure 3. Break-Before-Make (DG9426)
Document Number: 71807
S09-1675-Rev. E, 31-Aug-09
www.vishay.com
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