DG9424/9425/9426
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
S
V
L
V-
V
IN
Level
Shift/
Drive
V+
GND
D
V-
FIGURE 1.
TEST CIRCUITS
V
L
V+
Logic
Input
V
INH
50%
V
INL
t
r
<5 ns
t
f
<5 ns
t
OFF
V
L
V
IN
NO or NC
IN
GND
V+
COM
V
OUT
V
OUT
R
L
300
W
C
L
35 pF
0V
t
ON
90%
0.9 x V
OUT
V-
Switch
Output
Switch
V-
C
L
(includes fixture and stray capacitance)
V
OUT
= V
IN
R
L
R
L
+ r
ON
Note:
Logic input waveform is inverted for switches that
have the opposite logic sense control
FIGURE 2.
Switching Time
V
L
V+
Logic
Input
V
IN1
V
IN2
NO
1
IN
1
NC
2
IN
2
GND
V-
COM
2
V
O2
Switch
Output
R
L1
300
W
R
L2
300
W
C
L2
35 pF
C
L1
35 pF
Switch
Output
0V
V
IN2
V
O2
0V
COM
1
3V
50%
0V
V
IN1
V
O1
V
O1
90%
90%
t
D
t
D
V-
C
L
(includes fixture and stray capacitance)
FIGURE 3.
Break-Before-Make (DG9426)
www.vishay.com
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Document Number: 71807
S-31267—Rev. C, 16-Jun-03
VISHAY [ VISHAY TELEFUNKEN ]
